About Me
Hi, I'm Melih — an FPGA Engineer specializing in nanoseconds-level high-frequency trading systems. My expertise spans ultra-low-latency networking, PCIe architecture, and FPGA-accelerated custom designs. While my core focus is on hardware design and RTL synthesis, I also develop software components to deliver integrated, high-performance solutions.
Skills & Technologies
Programming Languages
- Verilog/SystemVerilog
- Python
- C / C++
- CMake
- TCL
- VHDL
Tools
- Vivado
- Icarus Verilog
- Verilator
Linting & Formatting
- Verible
Version Control
- Git
FPGA Platforms
- Xilinx
- Cisco
FPGA Projects
MAC-PCS Design
A complete ultra-low-latency MAC-PCS solution, working with competitive latencies in the industry.
SystemVerilog, Cocotb
Network Stack Design
Developed TCP and UDP offload engines working with the industry standards.
SystemVerilog, Cocotb
PCIe Design
Implemented QDMA (Queue Direct Memory Access). The design supports low-latency and high-throughput data transfers. It includes specialized channels for offloading the MAC-PCS and Network Stack.
SystemVerilog, Cocotb
Custom Framework Design
Designed a custom framework that puts MAC-PCS, Network Stack, and PCIe Designs together.
SystemVerilog, Cocotb
High-Frequency Trading Systems
Implemented MoldUDP, SoupBinTCP, ITCH, and OUCH communication protocols. Engineered custom trading logics on FPGA.
SystemVerilog, Cocotb
Software Projects
PCIe Driver
Designed a PCIe driver that matches with the expectations of FPGA and requirements of the kernel. Implemented kernel-bypassing techniques to achieve the lowest possible latency.
C/C++, Linux Kernel
Socket Design
Designed a socket for the software to enable the UDP/TCP offloading on FPGA.
C/C++, Linux Kernel
High-Frequency Trading Systems
Took part in a development of high frequency system in the software team.
C/C++, Linux Kernel
Contact
Email: aktopmelih@gmail.com
GitHub: mlhktp
LinkedIn: melih-aktop